1. Field of the Invention
The present invention relates to a semiconductor memory device provided with an I/O clamp circuit. More specifically, the present invention relates to a semiconductor memory device including an I/O clamp circuit for clamping a pulled up or pulled down node of an I/O line pair for applying an output signal of a sense amplifier included in a DRAM to a preamplifier.
2. Description of the Background Art
FIG. 8 is a schematic circuit diagram of an I/O line clamp circuit in a conventional DRAM. Referring to FIG. 8, a plurality of sense amplifiers 10 are connected through a plurality of transfer gates 20 to one end of an I/O line pair. Transfer gate 20 is turned on and off in response to a column selection line signal. The other end of I/O line pair 21 is connected to an input of a preamplifier 12. Preamplifier 12 amplifies a signal connected to I/O line pair 21, as I/O line pair 21 is relatively long and hence has a large capacitance and sense amplifier 10 has small drivability. Preamplifier 12 is an analog circuit and therefore it is necessary to appropriately set an input bias. Therefore, a pull up circuit 30 is connected between I/O line pair 21. Pull up circuit 30 is generally formed by a series connection of two MOS transistors. When a read signal, a write signal or a standby signal at a logical high ("H") level is input to NOR gate 31, pull up circuit 30 is turned off by an output from NOR gate 31.
Further, a clamp circuit 40 is connected to I/O line pair 21 so that charges are not left on I/O line pair 21 due to negative bump of a power supply voltage in the standby state. Clamp circuit 40 includes a clamp signal generating circuit including an n channel MOS transistor 41 having relatively long channel length L and very small supplying capability and p channel MOS transistors 42 and 43 having relatively large supplying capability connected in series between a power supply and a ground, and two n channel MOS transistors 44 and 45 connected in series between the pair of I/O lines 21. In the clamp generating circuit, two n channel MOS transistors are connected in series. However, the number of stages may be changed in accordance with the clamp voltage.
FIGS. 9A to 9D are time charts related to the operation of the I/O clamp circuit shown in FIG. 8. The operation of the I/O clamp circuit shown in FIG. 8 will be described with reference to FIGS. 9A to 9D.
Referring to FIG. 9A, while the standby signal is at the "H" level, that is, in the standby state, potential of I/O line pair 21 is kept at 2 Vthp as shown in FIG. 9D by the function of clamp circuit 40, provided that power supply voltage changes from Vcc1 to Vcc2 at time T1 and it changes from Vcc2 to Vcc1 at time T2.
Assuming that standby signal is switched from "H" to "L" level at time T3 and is activated, n channel MOS transistors 44 and 45 are turned off, the output from NOR gate 31 attains to the "HI" level and pull up circuit 30 operates. Accordingly, the potential of I/O line pair 21 attains to Vcc1-Vth.
When read signal represented by FIG. 9B attains to "H" level at time T4, pull up circuit 30 is turned off, a column selection line is selected and data of the selected sense amplifier 10 appears on I/O line pair 21 through transfer gate 20. Input bias of preamplifier 12 is at an appropriate value (Vcc1-Vth).
An operation when power supply voltage Vcc fluctuates in the active state will be described. Assuming that power supply voltage Vcc changes from Vcc1 to Vcc2 at time T5, the potential of I/O line pair 21 rises to Vcc2-Vth by the function of pull up circuit 30. When power supply voltage Vcc returns from Vcc2 to Vcc1 at time T6, I/O line pair 21 is kept at the potential of Vcc2-Vth as shown in FIG. 9D, as the pull up circuit 30 has single directivity, that is, it operates only in the direction of increasing the potential of I/O line pair 21 and clamp circuit 40 is not in operation. When a reading operation is performed at time T7, I/O line pair 21 is opened, referring to the potential Vcc2-Vth. Here, optimal input bias for preamplifier 12 is Vcc1-Vth, and therefore operation margin of preamplifier 12 will not be ensured.
Therefore, though the conventional clamp circuit is effective against fluctuation of Vcc in the standby state, it is not effective against fluctuation of Vcc in the active state.